The present invention relates generally to integrated circuits and in particular the present invention relates to integrated circuit packaging.
Integrated circuits (IC""s) are made up of electronic components linked together by conductive connections to form one or more functional circuits. IC""s are typically formed in a piece of silicon called a chip or die. Silicon dice can be formed in a wafer that is a sheet of silicon with a surface that is subject to a series of fabrication steps to form a pattern of identical IC""s. The IC""s are separated from each other by a repeating pattern of scribe lines, also called saw lines, in the surface of the wafer that serve as boundaries between the dice. One IC is formed in each die. At a stage in a fabrication process the dice are diced (cut apart) from the wafer along the scribe lines and each die is bonded to a substrate to form an IC package.
A substrate is a relatively flat and rigid structure that provides mechanical support for the die in the IC package, transmits signals to and from the IC, and can also transfer heat that is generated during the operation of the IC. The substrate may also be called a carrier. The substrate includes conductive leads connected to respective bonding pads on the die so that the IC may exchange signals with other circuits in the IC package and circuits connected to the IC package. Additional elements such as resistors and capacitors that are not readily included in the IC may be attached to the top or bottom of the IC package. The IC package may be applied to a circuit board assembly that comprises systems of interconnected IC packages to form an electronic device such as a computer or a cellular phone.
One method of bonding a die to a substrate in an IC package is called a flip-chip bonding method. One version of the flip-chip bonding method is formally known as the controlled collapse chip connection or C4 method. In the flip-chip bonding method, solder bumps are placed on bonding pads on the dice while they are connected together in the wafer. The wafer is then diced to separate the dice. Each die is then turned over, or flipped, and aligned with a corresponding pattern of bonding pads or solder bumps on a substrate. A second reflow procedure is carried out to join the bumps to form a series of solder columns between the die and the substrate. The solder columns serve as conductive connections or leads between an IC in the die and the substrate through which I/O signals are transmitted, and power is delivered
As microelectronic products move toward greater levels of integration, increasing functionality, and enhanced performance, the complexity of packaging technology grows in direct proportion. For example, the evolution of silicon processes into finer and finer feature sizes has resulted in microprocessor designs that are capable of achieving higher system clock speed and faster rise times.
As a result, the level of integration and the density of interconnects between integrated circuits, such as processor chips, and substrates has been increased tremendously. Thus, coupling the integrated circuits to a substrate for electrical and physical connectivity to external devices provides increased challenges as the interconnect density increases.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for new substrate technologies with enhanced interconnect density.
The above mentioned problems with integrated circuit packaging and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, an integrated circuit package comprises an integrated circuit die, an organic multi-layer substrate and T-shaped conductive pins. The organic multi-layer substrate comprises a dielectric base layer, and first conductor, first dielectric, and second conductor layers respectively fabricated on a top and a bottom of the dielectric base layer. The T-shaped conductive pins are soldered to an outer most conductor layer located on a bottom of the substrate.
In another embodiment, a microprocessor package comprises a microprocessor die, an organic multi-layer substrate and T-shaped conductive pins. The organic mult-layer substrate comprises a dielectric base layer, a first conductor layer fabricated on a top and a bottom of the dielectric base layer, a first dielectric layer fabricated on the first conductor layer, a second conductor layer fabricated on the first dielectric layer, a second dielectric layer fabricated on the second conductor layer, and a third conductor layer fabricated on the second dielectric layer. The organic multi-layer substrate thereby has at least eleven layers, of which six layers are conductor material. The T-shaped conductive pins are soldered to the third conductor layer located on a bottom of the substrate.
In yet another embodiment, a method of fabricating an integrated circuit substrate is provided. The method comprises forming a first conductive layer on a base dielectric layer, forming a first dielectric layer on the first conductive layer, forming a first via through the first internal dielectric layer using a laser to expose the first conductive layer, and forming a second conductive layer on the first internal dielectric layer. The second conductive layer coats the interior surface of the first via to form conductive paths through the first dielectric layer.